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PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
* Maximized EMI suppression using Cypress's Spread Spectrum Technology * Low jitter and tightly controlled clock skew * Highly integrated device providing clocks required for CPU, core logic, and SDRAM * Three copies of CPU clock at 66/100 MHz * Nine copies of 100-MHz SDRAM clocks * Eight copies of PCI clock * Two copies of synchronous APIC clock * Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock * Two copies of 66-MHz fixed clock * One copy of 14.31818-MHz reference clock * Power-down control * I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps APIC, 48MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps CPU, 3V66 Output Skew: ............................................175 ps PCI Output Skew: ........................................................500 ps CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns PCI to APIC Skew: .....................................................0.5 ns Table 1. Pin Selectable Functions SEL1 0 0 1 1 SEL0 0 1 0 1 Function Three-state Test 66-MHz CPU 100-MHz CPU
Block Diagram
VDDQ3
Pin Configuration
REF/APICDIV VDDQ3 X1 X2 GND GND 3V66_0 3V66_1 VDDQ3 VDDQ3 PCI0_ICH PCI1 PCI2 GND PCI3 PCI4 GND PCI5 PCI6 PCI7 VDDQ3 VDD3 GND GND USB DOT VDDQ3 SEL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND APIC0 APIC1 VDDQ2 CPU0 VDDQ2 CPU1 CPU2_ITP GND GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND DCLK VDDQ3 PWRDWN# SCLK SDATA SEL1
X1 X2
XTAL OSC
PLL REF FREQ
REF/APICDIV
VDDQ2
SDATA SCLK
I2C Logic
Divider, Delay, and Phase Control Logic
2
CPU0:1 CPU2_ITP APIC0:1 VDDQ3
W147G
2
SEL0:1
PLL 1
2
3V66_0:1
PCI0_ICH
7
PCI1:7
DCLK PWRDWN#
8
SDRAM0:7
PLL2
VDDQ3 USB DOT
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 13, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name REF/APICDIV Pin No. 1 Pin Type I/O Pin Description
W147G
Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually turned off via I2C interface. 66-MHz Clock Output: 3.3V fixed 66-MHz clock. USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs. Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal. Clock Function Selection pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions. Power Down Control: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface and integrated test port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration of SEL0:1. Voltage swing set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be individually turned off via I2C interface. Sychronous APIC Clock Outputs: Clock outputs running divide synchronous with the PCI clock outputs. Output frequency is controlled by the strap option on REF. Voltage swing set by VDDQ2. Data pin for I2C circuitry. Clock pin for I2C circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
X1 X2 PCI0_ICH, PCI1:7 3V66_0:1 USB DOT SEL0:1 PWRDWN# CPU2_ITP, CPU0:1 SDRAM0:7, DCLK APIC0:1
3 4 11, 12, 13, 15, 16, 18, 19. 20 7, 8 25 26 28, 29 32 49, 52, 50
I I O O O O I I O
46, 45, 43, 42, 40, 39, 37, 36, 34 55, 54
O O
SDATA SCLK VDDQ3
30 31 2, 9, 10, 21, 27, 33, 38, 44 22 51, 53 5, 6, 14, 17, 23, 24, 35, 41, 47, 48, 56
I/O I P
VDD3 VDDQ2 GND
P P G
2
PRELIMINARY
VDD
W147G
Output Strapping Resistor Series Termination Resistor Clock Load
10 k (Load Option 1) W147G Power-on Reset Timer Output Buffer Output Three-state
Q
Hold Output Low
D
10k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W147G is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel(R) architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation REF/APICDIV is a dual purpose l/O pin. Upon power-up the pin acts as a logic input. If the pin is strapped to a LOW state externally, APIC clock outputs will run divide synchronously at half PCI clock speed. If it is pulled HIGH, APIC clock will run synchronous to PCI clocks. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. Table 2. CK Whitney Truth Table SEL1 0 0 1 1 SEL0 0 1 0 1 CPU Hi-Z TCLK/2 66 MHz 100 MHz SDRAM Hi-Z TCLK/2 100 MHz 100 MHz 3V66 Hi-Z TCLK/3 66 MHz 66 MHz
After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Pin Selectable Functions Table 1 outlines the device functions selectable through SEL0:1. Specific outputs available at each pin is detailed in Table 2 below. The SEL0 pin requires a 220 pull-up resistor to 3.3V for the W147G to sense the maximum host bus frequency of the processor and configure itself accordingly.
PCI Hi-Z TCLK/6 33 MHz 33 MHz
48MHz Hi-Z TCLK/2 48 MHz 48 MHz
REF Hi-Z TCLK 14.318 MHz 14.318 MHz
APIC[1] Hi-Z TCLK/6 16.67 MHz 16.67 MHz
Notes 2 4, 5 3, 6, 7 3, 6, 7
Notes: 1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin. 2. Provided for board level "bed of nails" testing. 3. "Normal" mode of operation. 4. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 5. Required for DC output impedance verification. 6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
3
PRELIMINARY
Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W147G when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock,
10 ns 20 ns
W147G
respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs.
0 ns
30 ns
40 ns
CPU 66-MHz
C PU 66 Pe riod
SDRAM 100-MHz
S D R A M 1 0 0 P erio d
3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 33-MHz
Hu b-P CI
Figure 2. Group Offset Waveforms (66-MHz CPU Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
CP U 10 0 P eriod
SDRAM 100-MHz
SD R A M 10 0 P e rio d
3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 33-MHz
H ub-P CI
Figure 3. Group Offset Waveforms (100-MHz CPU Clock)
4
PRELIMINARY
Power Down Control
W147G
W147G provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW.
0ns
25ns
50ns
75ns Center
1 VCO Internal CPU 100MHz 3V66 66MHz PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz
2
Figure 4. W147G PWRDWN# Timing Diagram[8, 9, 10, 11] Table 3. W147G Maximum Allowed Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2 = 2.625V All static inputs = VDDQ3 or VSS 100 A 70 mA 100 mA Max. 3.3V supply consumption Max. discrete cap loads VDDQ3 = 3.465V All static inputs = VDDQ3 or V SS 200 A 280 mA 280 mA
W147 Condition Powerdown Mode (PWRDWN# = 0) Full Active 66 MHz SEL1,0 = 10 (PWRDWN# =1) Full Active 100 MHz SEL1,0 =11 (PWRDWN# = 1)
Notes: 8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW transition. 9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G. 10. The shaded sections on the SDRAM, REF, and USB clocks indicate "don't care" states. 11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
5
PRELIMINARY
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5. As shown in Figure 5, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W147G
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 6. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the I2C data stream. Refer to page 8 for more details.
EMI Reduction
Spread Spectrum Enabled NonSpread Spectrum
Figure 5. Typical Clock and SSFTG Comparison
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN.
Figure 6. Typical Modulation Profile
6
100%
PRELIMINARY
1 bit Start bit 7 bits Slave Address 1 R/W 1 Ack 8 bits Command Code 1 Ack
W147G
Byte Count = N
Ack 1 bit
Data Byte 1 8 bits
Ack 1
Data Byte 2 8 bits
Ack 1
...
Data Byte N 8 bits
Ack 1
Stop 1
Figure 7. An Example of a Block Write[12] Serial Data Interface The W147G features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transTable 4. Example of Possible Byte Count Value Byte Count Byte MSB 0000 0000 0000 0000 0000 0000 0000 0000 0010 LSB 0000 0001 0010 0011 0100 0101 0110 0111 0000 Not allowed. Must have at least one byte. Data for functional and frequency select register (currently byte 0 in spec) Reads first two bytes of data. (byte 0 then byte 1) Reads first three bytes (byte 0, 1, 2 in order) Reads first four bytes (byte 0, 1, 2, 3 in order) Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13] Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13] Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) Max byte count supported = 32 Notes fer a maximum of 32 data bytes. The slave receiver address for W147G is 11010010. Figure 7 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W147G expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 4 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W147G. However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 5. Serial Data Interface Control Functions Summary Control Function Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Enables or disables spread spectrum clocking. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For EMI reduction.
Spread Spectrum Enabling (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0. duction device testing.
Notes: 12. The acknowledgment bit is returned by the slave/receiver (W147G). 13. Data Bytes 3 to 7 are reserved.
7
PRELIMINARY
W147G Serial Configuration Map
1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0= Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 26 25 49 Reserved Reserved Reserved Reserved Spread Spectrum (1=On/0=Off) DOT USB CPU2_ITP Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
W147G
2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. 4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte 7 are reserved and must be written to "zero."
Byte 1: Control Register (1 = Enable, 0= Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 36 37 39 40 42 43 45 46 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Byte 2: Control Register (1 = Enable, 0= Disable)[14] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 18 16 15 13 12 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Reserved Name (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description
Note: 14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.
8
PRELIMINARY
DC Electrical Characteristics
DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter VDD3 VDDQ2 VDDQ3 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage 3.3V Supply Voltage Storage Temperature Min. -0.5 -0.5 -0.5 -65 Max. 4.6 3.6 4.6 150
W147G
Unit V V V C
Absolute Maximum DC I/O Parameter Vih3 Vil3 ESD prot. Description 3.3V Input High Voltage 3.3V Input Low Voltage Input ESD Protection Min. -0.5 -0.5 2000 Max. 4.6 Unit V V V
DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V5% Vih3 Vil3 Iil VDDQ2 = 2.5V5% Voh2 Vol2 VDDQ3 = 3.3V5% Voh3 Vol3 VDDQ3 = 3.3V5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance 0 0 13.5 Ioh=(-1 mA) Iol=(1 mA) 2.4 0.55 5 22.5 6 7 70 V V pF pF pF nH C 3.3V Output High Voltage 3.3V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh=(-1 mA) Iol=(1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current
[15]
Description 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 2.5V I/O Supply Voltage
Condition 3.3V5% 3.3V5% 2.5V5% VDD3 0Min. 3.135 3.135 2.375 2.0 VSS-0.3 -5
Max. 3.465 3.465 2.625 VDD+0.3 0.8 +5
Unit V V V V V A
Ambient Temperature No Airflow Ta Note: 15. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
9
PRELIMINARY
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off
W147G
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[16] 66.6-MHz Host Parameter TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL TPeriod THIGH TLOW TRISE TFALL tpZL, tpZH tpLZ, tpZH Description Host/CPUCLK Period Host/CPUCLK High Time Host/CPUCLK Low Time Host/CPUCLK Rise Time Host/CPUCLK Fall Time SDRAM CLK Period SDRAM CLK High Time SDRAM CLK Low Time SDRAM CLK Rise Time SDRAM CLK Fall Time APIC CLK Period APIC CLK High Time APIC CLK Low Time APIC CLK Rise Time APIC CLK Fall Time 3V66 CLK Period 3V66 CLK High Time 3V66 CLK Low Time 3V66 CLK Rise Time 3V66 CLK Fall Time PCI CLK Period PCI CLK High Time PCI CLK Low Time PCI CLK Rise Time PCI CLK Fall Time Output Enable Delay (All outputs) Output Disable Delay (All outputs) Min. 15.0 5.2 5.0 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.3 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 15.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 100-MHz Host Min. 10.0 3.0 2.8 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.3 0.4 0.4 15.0 5.25 5.05 0.5 0.5 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. 10.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 N/A N/A N/A 2.0 2.0 10.0 10.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16, 17 19 20 16, 18 19 20 16 19 20 16 19 20 Notes 16 19 20
All Clock Stabilization from Power-Up 3 3 ms tstable Notes: 16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 17. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 18. TLOW is measured at 0.4V for all outputs. 19. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 20. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
10
PRELIMINARY
Group Skew and Jitter Limits Output Group CPU SDRAM APIC 48MHz 3V66 PCI REF Pin-Pin Skew Max 175 ps 250 ps 250 ps 250 ps 175 ps 500 ps N/A Cycle-Cycle Jitter 250 ps 250 ps 500 ps 500 ps 500 ps 500 ps 1000 ps Duty Cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 Nom Vdd 2.5V 3.3V 2.5V 3.3V 3.3V 3.3V 3.3V
W147G
Skew, Jitter Measure Point 1.25V 1.5V 1.25V 1.5V 1.5V 1.5V 1.5V
Output Buffer Clock Output Wave
Test Point
Test Load TPERIOD Duty Cycle THIGH
2.0
2.5V Clocking Interface
1.25 0.4
TLOW TRISE TFALL TPERIOD Duty Cycle THIGH
2.4
3.3V Clocking Interface
1.5 0.4
TLOW TRISE TFALL
Figure 8. Output Buffer
Ordering Information
Ordering Code W147G Package Name H Package Type 56-pin SSOP (300 mils)
Intel is a registered trademark of Intel Corporation. Document #: 38-00820
11
PRELIMINARY
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
W147G
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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